FIG. 1 shows an implementation of a typical digital circuit. logic blocks 11, 13, etc., implement boolean logic functions on data that is stored in latch blocks 10, 12, 14, etc. A global clock signal synchronizes all latches so that data transfer from block 10 to 11 to 12 to 13 to 14 etc. proceeds in a uniform manner. Nearly all modern microprocessors, as well most other digital circuits, have this structure.
There are many ways in which logic blocks can be implemented. The most flexible approach is to use static logic. FIG. 2 shows a static logic implementation of Q=A * B+not.sub.-- A * not.sub.-- B (this is a CMOS technology example). Gate I1 inverts the logic value of input A and gate I2 inverts the logic value of input B. For example, when A is at logic level `1` (VDD) transistor N1 conducts and transistor P1 does not conduct. This forces node not.sub.-- A to logic level `0` (GND). When A is at logic level `0` transistor P1 conducts and transistor N1 does not conduct. This forces node not.sub.-- A to logic level `1`. So when both nodes A and B are at logic level `1` transistors N4 and N6 conduct while transistors P4 and P6 do not conduct. This pulls node S to `0`. Inverter I3 complements the value of node S. This generates A * B in the above equation. The table below shows the state of each node and transistor in FIG. 2 for each of the four possible combinations for signals A and B (ON means transistor is conducting while OFF means transistor is not conducting).
__________________________________________________________________________ A B .vertline. not.sub.-- A not.sub.-- B N3 N4 N5 N6 P3 P4 P5 P6 S .vertline. Q __________________________________________________________________________ 0 0 .vertline. 1 1 ON OFF ON OFF OFF ON OFF ON 0 .vertline. 1 0 1 .vertline. 1 0 ON OFF OFF ON OFF ON ON OFF 1 .vertline. 0 1 0 .vertline. 0 1 OFF ON ON OFF ON OFF OFF ON 1 .vertline. 0 1 1 .vertline. 0 0 OFF ON OFF ON ON OFF ON OFF 0 .vertline. 1 __________________________________________________________________________
The strength of the NFET and PFET transistors is controlled by their physical width: the wider the transistor the stronger it is. The strength, in turn, controls the delay characteristics of the associated gates. For example, if N1 in gate I1 is twice the strength of P1, then as node A undergoes a `0` to `1` transition gate I1 will pull down node not.sub.-- A to logic level `0` twice as fast as when node A undergoes a `1` to `0` transition and gate I1 has to pull up node not.sub.-- A to logic level `1`. Since when using static gates there is an equal chance between any given signal undergoing a `0` to `1` transition as it is for that signal to undergo a `1` to `0` transition, NFET and PFET transistors are sized with equal strength. This gives the best overall average gate delay. If it is known that signals can only transition unidirectionally (either only `0` to `1` or only `1` to `0`) at predetermined times then gate delay can be made smaller by using one of either preset static or dynamic gates.
FIG. 3 is an example of a preset static gate designed under the assumption that inputs A, B, not.sub.-- A, and not.sub.-- B can only undergo `0` to `1` transitions. By taking advantage of this information, transistors N3, N4, N5, N6, and P7 can be made stronger as compared to transistors P3, P4, P5, P6, and N7. This allows the preset static gate to switch faster. Note that output Q also undergoes a `0` to `1` transition. Thus, one preset static gate can drive another preset static gate and maintain unidirectional transitions. Eventually, inputs A, B, not.sub.-- A, and not.sub.-- B will all undergo a `1` to `0` transition. However, since transistors P3, P4, P5, P6, and N7 are all weak it may take a long time for node S to go to logic level `1` and node Q to go to logic level `0`. To reduce this transition time, two more transistors (P8 and N8) are added to the circuit of FIG. 3, as shown in FIG. 4. In the circuit of FIG. 4, When CLOCK=`1` P8 does not conduct, while N8 conducts. The circuit switches when either A and B or not.sub.-- A and not.sub.-- B undergo `0` to `1` transition. When CLOCK=`0` N8 does not conduct and P8 conducts. P8 helps to restore node S to `1` and node Q to `0`.
The circuit of FIG. 4 can be made even faster by eliminating transistors P3, P4, P5, and P6, as shown in FIG. 5. This is a dynamic gate. Node S is precharged to logic level `1` by transistor P8 when CLOCK=`0`. When CLOCK=`1`, if either A and B or not.sub.--A and not.sub.-- B undergo a `0` to `1` transition, node S goes to `0` and node Q goes to `1`.
The main advantage of preset static and dynamic gates over static gate is that preset static and dynamic gates switch faster. When used throughout a digital system, however, these types of latches complicate the design due to three factors:
1. Circuits must be arranged in such a way that only unidirectional transitions are allowed in the critical paths. PA1 2. The Clock needs to be wired not only to latches as shown in FIG. 1, but also to all logic gates. PA1 3. More global wires are needed for routing in the system. In FIG. 2, complements of A and B are made locally. In FIGS. 4 and 5, all signals can undergo only `0` to `1` transition. This precludes local generation of required complement values, and signals not.sub.-- A and not.sub.-- B must be generated in the same block that A and B are generated in and brought in on global wires.
At present, many digital circuits are designed completely with static circuits. Such designs experience long delays in the multiplexers that feed the latches. Other designs use dynamic circuits and try to manage the increase in complexity. It is clear, however that neither of these solutions is completely satisfactory, and that an improved scheme would be extremely desirable.